The present invention relates to the field of flash memory construction. More specifically, one embodiment of the present invention provides an improved method and apparatus for addressing flash memory cells.
Flash electrically erasable programmable read-only memory (EEPROM) has been an increasingly popular choice for memory systems architects because of the densities that can be achieved. For example, as much as sixteen megabytes of flash memory can be found on a single chip, such as the 29LV160 flash memory chip made by Hyundai Electronics America of San Jose, Calif. One feature of flash memories which allows such density is that each cell of the memory requires the use of only a single transistor. A cell is the unit of memory in which a bit is stored, or multiple bits in the case of multi-bit cells. As is well known in the art of flash memories, one or more bits can be stored as a charge on a floating gate interposed between a control gate and the source/channel/drain of the single transistor of a cell. Typically, a word line is connected to the control gates of each flash memory cell in a row of memory and a bit line is connected to the drains of each flash memory cell in a row of cells. The sources of each of the cells are coupled to a reference, typically ground; however, in some memories the connections for sources and drains are reversed.
To address a particular cell, a word line associated with the particular cell's row is activated to activate a row of the memory and a bit line associated with the particular cell's column is used to perform a memory operation. Multiple cells in a row can be operated on in parallel, using multiple bit lines. The memory operations performed on a selected cell or row of cells include reading the data stored in the cell or cells and programming, i.e., writing, a value or values to the cell or cells. Another memory operation, erasing, might also be performed on a particular cell, but more typically more than one row are erased at one time, hence the name "flash" memory. The term "sector" is used to describe a set of cells which are erased as a group in a flash memory. One disadvantage to this addressing scheme is that, when data is read from or written to the cell, the activity on the bit line may disturb the contents of cells in rows that have not been selected, as the bit line is coupled to many unselected cells in unselected rows in addition to a selected cell in the selected row. In flash memories where the drains of each cell are coupled to a bit line, this undesired effect is often referred to as a "drain disturb" effect.
In response to drain disturb and other concerns, some memory chips have been designed with a page architecture to reduce the ratio of unselected cells to selected cells on a given bit line. One example of this is shown in U.S. Pat. No. 5,126,808 (which is incorporated by reference herein for all purposes). That reference shows the division of the rows of a flash memory into a plurality of pages wherein a column of cells overlies a plurality of pages and a page bit line is provided for each column in each page. Using this approach, if one row is selected, only the page bit line for the page containing the selected row need be activated. This allows for the cells in other pages to remain undisturbed, as their page bit lines are not activated. This reduces the number of times an inactivated cell is disturbed, and consequently increases the number of times the memory can be accessed before drain disturb errors occur.
Another desire in flash memories is to increase the access speed. The apparatus shown in U.S. Pat. No. 5,126,808 may reduce the effects of drain disturb, but it does not provide for simultaneously accessing memory locations. Therefore, what is needed is an improved flash memory architecture which provides for improved access times.